Protection circuit for an integrated circuit

ABSTRACT

The invention is directed to a protective circuit for an integrated circuit  1 . This protective circuit is preferably arranged in a plurality of circuit levels  2, 3  under and/or above the intergrated circuit  1 . It exhibits a plurality of interconnects  10, 11  that are charged with different signals of one or more signal generators. The different signals, after traversing the interconnects  10, 11 , are analyzed with one or more detectors in that the signals received by detectors are respectively compared to rated reference signals, and an alarm signal is forwarded to the integrated circuit given the presence of a significant difference. On the basis of this alarm signal, the integrated circuit is switched into a security mode that makes an analysis or a manipulation of the integrated circuit practically impossible.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention is directed to a protective circuit for an integratedcircuit.

2. Description of the Related Art

Certain forms of electronic circuits, particularly integrated circuitsfor use in chip cards, require a high degree of secrecy of circuitinformation or of internal chip data. This security-relevant informationmust be protected both against foreign analysis as well as againstmanipulation.

Various approaches have been used to achieve this protection. Forexample, integrated circuits have been provided with a metallic sleeveof, for example, silver or titanium which can prevent a readout of theintegrated circuits with X-rays. A further approach has been to arrangean interconnect in the highest circuit level of an integrated circuit asshield line and to monitor the physical properties such as theresistance, the capacitance, etc., thereof. When a change is detected,for example, due to short-circuiting, grounding or parting duringundesired observation or manipulation, an alarm signal is thentriggered. Such a protective circuit is disclosed by U.S. Pat. No.5,389,738. These types of protective circuits, however, are inadequatesince the anticipated physical properties can be simulated with suitableexternal measures and the protective circuit can consequently not detectan outside attack by observation or manipulation and, thus, no suitablecounter-measures can be taken.

SUMMARY OF THE INVENTION

The invention is based on the object of specifying a protective circuitfor integrated circuits that provides greater protection againstunwanted observation or manipulation.

This object is achieved by a protective circuit for an integratedcircuit, wherein the protective circuit is arranged in a circuit levelat a location under or above the integrated circuit, the protectivecircuit comprising a plurality of interconnects that are charged withdifferent signals of a signal generator, a detector that evaluates thedifferent signals transmitted via the plurality of interconnects forfaulty behavior, the detector having an output at which, when the faultybehavior is found, a control signal is provided for switching theintegrated circuit into a security mode.

The inventive protective circuit is arranged in at least one circuitlevel above or below the integrated circuit as well. This protectivecircuit thereby exhibits one or more interconnects that are charged withsignals that change over time or with different signals as well. Thesesignals are transmitted via the interconnects and are subsequentlyinvestigated by the detector or detectors in that the received signal tobe investigated is respectively compared to a reference signal, i.e.,the anticipated signal. When one or more detectors find a significantdeviation, then this triggers an alarm signal that switches theintegrated circuit into a security mode. In this mode, for example, thecontent of the memory cells can be erased, so that the control programsand the stored data can no longer be read out and interpreted.

By employing a plurality of different signals that are conducted over aplurality of interconnects and subsequently analyzed by the variousdetectors, it is nearly impossible to supply all alarm-triggeringsignals in the correct way from the outside during an attempted readoutor manipulation and to simulate the presence of these signals for thedetectors. When, for example, the integrated circuit is planarlymechanically eroded from above such that it is possible to view thecircuit levels of the integrated circuit lying therebelow, then theinterconnects of the protective circuit lying above are affected first,which leads to a modification or, to an interruption of the signaltransmission that is detected by one or by several detectors. This isalso true when individual interconnects are tapped with miniatureneedles, resulting in modifications of, for example, the signal shape,the signal attenuation or the like. All of these modifications thenregularly cause an error recognition by various detectors.

Inventively, thus, it is not only a single signal but a plurality ofdifferent signals that must be simulated. Precisely in view of theextremely limited spatial conditions of an integrated circuit, it isnearly impossible to specifically supply this plurality of simulatedsignals to the various detectors. A nearly all-embracing protection ofthe integrated circuit by the protective circuit arranged above is thusestablished.

Preferably, the integrated circuit is surrounded in a sandwich-likemanner by a protective circuit above and a protective circuit below theintegrated circuit, so that an observation or manipulation from bothabove as well as below is precluded by the protective circuits.

It has proven successful to fashion the detectors such that, in theevaluation of the transmitted signals, these signals are investigatedfor integrity, which can especially ensue with a CRC check, with achecksum comparison, with a parity check or with other signaturecomparisons. As a result of this integrity comparison between thetransmitted signal and the integrity value of the anticipated signal,also referred to as reference signal, it is possible to prevent amanipulation of the protective circuit in which the detector isquasi-shorted, whereby one and the same signal is forwarded both asreference signal and as transmitted signal to the detector with a mereidentity comparison for detecting improper behavior.

The different signals that are supplied to the different interconnectscan be realized with a common signal generator or can also be realizedby a plurality of individual signal generators. Preferably, thegenerator or generators is/are in communication with the detectorsresulting in the respective detector receiving information about thetype and nature of the anticipated signal, (the reference signal,) fromthe generator allocated to it. It is thus possible that the generatorsdynamically modify their output signals and inform the detectors of thismodification, which makes the simulation of the signals even moredifficult in an attack since the time curve of the signals is also takeninto consideration,

It has proven especially advantageous to extend the interconnects over aplurality of circuit levels, resulting in a significantly bettercoverage of the integrated circuit to be protected. Similar to the viewinto the structure of the integrated circuit over a plurality of circuitlevels (and, thus, a view into the type and nature of the generation, ofthe signal guidance and of the detection of the various signals) is alsosignificantly more difficult and is thereby not easy to simulateexternally. Consequently, each modification of the protective circuit byan intervention from the outside leads to a detection of the faultybehavior, since a simulation is extremely difficult or nearly impossibledue to the extremely difficult, three-dimensional structure of thefashioning of the interconnect or, the guidance therefor. It is thusclear that the one circuit level of the protective circuit protects theother circuit level of the protective circuit against an analysis. Anextremely far-reaching and dependable protective circuit for theintegrated circuit is definitely established by this approach.

According to a preferred embodiment of the protective circuit, theinterconnects of the protective circuit are fashioned such that,ideally, they largely completely planarly cover the integrated circuitto be protected. This is done in a manner such that, when lookingthrough the protective circuit onto the integrated circuit, there is nolonger any possibility of directly reaching the protective circuit, forexample, through bores or the like, i.e. without damaging theinterconnects of the protective circuit. This far-reaching or completecoverage is enabled in a simple and sure way by precisely fashioning theinterconnects over a plurality of circuit levels or in a plurality ofcircuit levels, since the interconnects can be arranged in a plane withadequate spacing from one another to prevent crosstalk. The regionbetween the interconnects can just be covered by interconnects in theother circuit level of the protective circuit, enabling a completecoverage of the integrated circuit or, respectively, of the criticalparts of this integrated circuit.

An attempt made to approach the integrated circuit, for example with abore, leads to damage to one of the interconnects, which leads to amodified signal. When the interconnect is fashioned with an extremelyslight interconnect width that corresponds to the size of such a bore oris smaller, then each such bore leads to an interruption of theinterconnect and, thus, to a fault signal that can be very reliablydetected. It is also possible that such a bores would lead to a shortbetween various interconnects, which can also be very dependablyrecognized as fault signal by the corresponding detectors as a totalsignal fade. The interconnect width is thereby preferably selected suchthat it corresponds to the minimum interconnect width given a specificchip technology employed. Due to these specific fashionings of theinterconnects as, on the one hand, very narrow interconnects and as, onthe other hand, interconnects extending over various circuit levels aswell as with optimum surface coverage, an extraordinary degree ofprotective effect against a mechanical intervention (e.g., boring orplaining) is established.

According to a preferred embodiment of the invention, the detector ordetectors of the protective circuit are arranged in a circuit levelunder the highest circuit level having interconnects of the protectivecircuit and are protected against unwanted access by theseinterconnects. A cascading protection for the detectors of theprotective circuits by the interconnects of the protective circuits andfor the integrated circuit by the interconnect with detectors isestablished by this systematic structure.

An observation or manipulation of the detector or detectors is preventedby this arrangement due to the lines lying above the detector(s), whichprecludes another possibility of an attack in which signals could bedirectly supplied into the detectors without proceeding via theinterconnects.

In a corresponding way, it is advantageous to arrange the generator orgenerators in a circuit level that is protected by interconnects of theprotective circuit lying above it. Such an arrangement of the detectorsor, respectively, of the generators definitely proves to be a criticalway of enhancing the protective effect of the protective circuit againstunauthorized access.

When the different signals are generated completely independently of oneanother, for example, by independent generators, then it is assured thatthese signals differ significantly in terms of their signal curve, sincethey do not systematically depend on one another. Such signals can onlybe simulated with extreme outlay and with extreme difficulty, especiallysince the plurality of different signals must be supplied in a targetedfashion into the correct interconnects or, respectively, the correctdetectors. This is nearly impossible given the extremely restrictedspatial dimensions of the integrated circuit. Such a protective circuithas proven particularly successful in protecting an integrated circuit.

In one version of the invention, a plurality of detectors are allocatedto one interconnect, these detectors tapping the signal on the oneinterconnect at a position specific to the respective detector andmonitoring it. In this construction, the interconnect is divided intoseveral interconnect sections that are each respectively monitored bydetectors allocated to them. These interconnect sections thus assume thefunction of a monitored interconnect. Over and above this, however, themultiple monitoring of the entire interconnect with the variousinterconnect sections assures that, if an intervention into thisinterconnect with suitable intervention measures were not to be detectedby one detector, the other detectors or some of the other detectors atthe overall interconnect will find a variation of the monitored signaland trigger an alarm. The redundant arrangement of the detectors at aninterconnect thus establishes an enhanced protective effect of theprotective circuit.

In general, it is desirable to provide optimally many signal lines andoptimally many signal generators or detectors that complicate an attackin the form of reconfiguration merely due to their number. Limits,however, are placed on the number of signal lines/generators/detectorsdependent on the size of the integrated circuit, since many discretesignals mean a high hardware expenditure, which leads to the circuitbecoming significantly more expensive due to these security measures.

In another version of the invention, the above-described method ofprotective signal generation is combined with a multiplexer and ademultiplexer, where different interconnects of the protective shieldare connected to the same generator outputs and detector inputs atdifferent times on the basis of a time-division multiplex method. Inthis way, the number of generators and detectors is smaller than thenumber of shield segments.

A further advantage of this arrangement is that the number of referencelines that supply the detectors with a reference signal from theappertaining detector is likewise reduced, which leads to a considerablesaving of chip area.

The multiplexers and demultiplexers can either be centrallysynchronously controlled or their status may be dependent only on theplurality of past clock cycles of the common clock system. A random orpseudo-random drive of the multiplexer channels is especiallyadvantageous. A true random drive requires an ongoing synchronization ofmultiplexer and demultiplexer with specific control signals. Apseudo-random drive allows a local generation of identical controlsignals in the respective spatial proximity of multiplexer anddemultiplexer.

According to an especially preferred embodiment of the protectivecircuit and given a plurality of detectors, the detectors are networkedwith one another.

What this achieves is that the integrated circuit is driven such as soonas one detector identifies a faulty behavior and, by inference, anunallowed attack on the integrated circuit that the intergrated circuitis switched into a comprehensive security mode. Via the networking, itis also possible that the individual detectors check thefunctionability/presence of the other detectors in the framework of anacknowledgment function or in the framework of a watchdog function andthereby recognize an unallowed intervention into the protective circuitor, respectively, the integrated chip and trigger the correspondingsecurity mode of the integrated circuit.

In addition to networking the detectors, it has also proven advantageousto network the generators, which permits recognition of a failureintervention in a generator. Over and above this, the networking of thegenerators with the detectors makes it possible for the generators toprovide the detectors allocated to them with information about thesignals they output, for example, about the time curve, about theirlevel, about their shape or the like. As a result thereof, thevariability of the different signals and, thus, the degrees of freedomof the protective circuit can be significantly enhanced, which makesintervention more difficult and thereby significantly enhances theprotective effect of the protective circuit against an unnoticed attackon the integrated circuit.

The inventive protective circuit thus exhibits the underlying idea ofdecentralization the components of the protective circuit are no longerlocally concentrated but instead are distributed over a larger spatialarea, multiplying in number and fashioning them in a differentiatedmanner. This permits the and the transport via the interconnects and themonitoring of the signals to be distributed onto a plurality ofredundant units, which leads to greater protection against an unnoticedobservation or manipulation of the protective circuit or respectively,of the integrated circuit to be protected.

BRIEF DESCRIPTION OF THE DRAWINGS

Inventively protective circuits for integrated circuits and theiradvantages are explained in greater detail below on the basis ofexemplary embodiments with the assistance of drawings.

FIG. 1 is schematic diagram showing a circuit structure of an inventiveprotective circuit with a signal generator and one signal detector perinterconnect;

FIG. 2 is a schematic diagram showing a circuit structure of anotherembodiment protective circuit;

FIG. 3 is a section view through an integrated circuit with protectivecircuit; and

FIG. 4 is a schematic diagram showing a circuit structure of a furtherinventive protective circuit with demultiplexer/multiplexerarrangements.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 schematically shows the structure of a protective circuit for anintegrated circuit. It shows three interconnects 10, 11, 12 that areseparated from one another and proceed parallel. These interconnects 10,11, 12 have a winding patter and cover a certain region in a circuitlevel of the integrated circuit.

The interconnects 10, 11, 12 are respectively connected to their ownsignal generator 20, 21, 22. Signals that are independent of one anotherand, thus, also fundamentally different are supplied into theinterconnects via the signal generators 20, 21, 22. The supplied signalstraverse the interconnects 10, 11, 12 and are analyzed at the end of theinterconnects 10, 11, 12 with a detector 30, 31, 32 allocated to eachinterconnect.

In the scope of this analysis, the different signals received via theinterconnects 10, 11, 12 are compared to the reference signal providedin via connecting lines 13, 14, 15 between the generators 20, 21, 22 andthe detectors 30, 31, 32 allocated to them. The reference signals eitherdirectly represent the signals the way they appear after traversing theinterconnects 10, 11, 12 or they provide the information needed in orderto determine the required information for the reference signals fromthem.

The evaluation in the detectors 30, 31, 32 ensues in that the referencesignals are compared to the arriving signals received via theinterconnects 10, 11, 12. When a difference is found, an alarm signal isgenerated as control signal for the integrated circuit and is conductedto the integrated circuit via the alarm line 4 allocated to eachdetector 30, 31, 32.

On the basis of this alarm signal, the integrated circuit is thenswitched into a condition that is referred to as a security mode. Inthis security mode, for example, the contents of the memory cells can nolonger be read out since, for example, they are completely erased afterthe switch into the security mode and the information contained thereinhas thus been irretrievably lost. This prevents reading out ormanipulating the important information of the integrated circuitcontained in program and data memories, for example, code Keys, PINnumbers or personal data of the user.

Due to the multiple, decentralized fashioning of the interconnects 10,11, 12, of the signal generators 20, 21, 22 and of the detectors 30, 31,32, it is extremely difficult to fool this protective circuit bysupplying external signals in order to obtain more detailed informationabout the integrated circuit to be protected, for example, on the basisof a planing process or drilling process or the like.

Due to the necessity of simulating not only one signal but of pluralityof different signals simultaneously at different locations for differentdetectors that are arranged on a very spatially limited region, it isnearly impossible to carry out an attack on the integrated circuitwithout determination of a signal modification and, thus, faultybehavior implying an attack on the protective circuit with theintegrated circuit to be protected. When a detector 30 detects a faultybehavior of the signal of the interconnect 10 supplied to it,then—independently of the other detectors 31, 32—it will forward analarm signal to the integrated circuit via the alarm line 4 and therebytrigger the security mode.

Due to the winding parallel pattern of the interconnects 10, 11, 12, alargely closed area-covering interconnect structure is established thatprotects the integrated circuit lying therefor, and or at least a regionof it against access through these interconnects 10, 11, 12. If someonewere to attempt to get at the integrated circuit lying under theinterconnects 10, 11, 12 with a mechanical means, then he would belargely forced to damage or entirely interrupt one of the interconnects10, 11, 12, which would lead to a significant change of the signaltransmitted via this interconnect. Such a significant change isidentified as faulty behavior by the detector 30, 31, 32 allocated tothis interconnect and the detector outputs a corresponding alarm signal.

The interconnects 10, 11, 12 are fashioned with such a narrowinterconnect width that any drilling for defeating the circuit levels 2,3 of the protective circuit leads to an interruption of an interconnect.To that end, it is necessary to select the spacing of the individualinterconnects 10, 11, 12 very small and to arrange the interconnects inthe circuit level or levels with a tight winding. An absolutely reliableinterruption due to an observation or manipulation to be prevented is infact established in that the signal on this interrupted interconnect 10,11, 12 is completely interrupted and interpreted as an attack.

The signals generated by the generators 20, 21, 22 are specific signals,usually digital but also analog, that allow a modification on thetransmission path via the interconnect 10, 11, 12 to appear clearly in asignal processing,

FIG. 2 schematically shows an embodiment of a further protectivecircuit. Here, a single interconnected interconnect structure isprovided that exhibits a feed point 9 for a signal formed by the onesignal generator 20 into the interconnect structure.

Four positions for outfeed of a signal transmitted via the interconnectstructure are provided at the interconnect structure. Each of theseoutfeed positions is provided with an amplifier 43, 44, 45, 46 foramplifying the outfed signal. These amplified signals are subsequentlysupplied to the detectors 33, 34, 35, 36. The interconnect structure,dependent on the respective tapping point, forms the interconnect 10 a,i.e., the interconnect structure between the feed point 9 and the tappoint of the amplifier 43 for the detector 33, the interconnect 10 bbetween the feed point 9 and the tap point defined by the amplifier 44for the detector 34, the interconnect 10 c between the feed point 9 andthe tap point for the amplifier 45 for the detector 35, and theinterconnect 10 d between the feed point 9 and the tap point for theamplifier 46 for the detector 36.

Each of the detectors works independently of the other detectors and candrive the integrated circuit via its alarm line 4 such that theintegrated circuit is switched into the security mode.

The generator 20 is connected via the connecting lines 16, 17, 18, 10 tothe detectors 33, 34, 35, 36 and provides these detectors with thespecific information for the reference signals for monitoring theinterconnect 10 a, 10 b, 10 c, 10 d. In a software-controlled manner,the generator 20 randomly selects the type of the infed signal andsignals the form of the infed signal to the detectors 33, 34, 35 via thecorresponding connecting lines 16, 17, 18, 19. The detectors 33, 34, 35interpret the signal supplied to them by the generator 20 via theconnecting line 16, 17, 18, 19 in that they compare this signal to thesignal of the interconnect 10 a, 10 b, 10 c, 10 d supplied from the tappoints. When a significant difference, i.e. a discrepancy, is found,then each detector 33, 34, 35, 36, independently of the others, outputsan alarm via its alarm line 4 which switches the integrated circuit intothe security mode.

What the overlapping, interconnected fashioning of the interconnect 10a. 10 b, 10 c, 10 d achieves is that an intervention in the interconnectof the interconnect system leads to modification of not only oneinterconnect 10 a, 10 b, 10 c, 10 d but to a modification of the signalon a plurality of interconnects 10 a, 10 b, 10 c, 10 d at the same time.In the case of an unwanted observation or manipulation, it is not onlythe signal of one detector but of a plurality of detectors, particularlyall detectors 33, 34, 35, 36, of this interconnect system that wouldhave to be charged with a simulated and correct signal. This signal mustcorrespond in shape and type and in time curve to the reference signalthat the generator 20 supplies via the connecting line 16, 17, 18, 19 tothe detectors 33, 34, 35, 36 either indirectly or directly. It is thusclear that the illustrated generator 20 is in theposition—software-controlled—to dynamically modify the signal fed in atthe feed point 9 and to thereby largely preclude the observation ormanipulation of the protective circuit and, thus, of the integratedcircuit 1 protected by the protective circuit.

FIG. 3 shows the layered structure of the integrated circuit 1 with theprotective circuit arranged above it. The illustration of acorresponding second protective circuit at the underside of theintegrated circuit is not shown in FIG. 3, but such a second protectivecircuit at the other side of the integrated circuit 1 has a structurecorresponding to that of the protective circuit shown here.

The protective circuit is arranged above the integrated circuit 1. Itexhibits two circuit levels 2, 3 lying above one another that areseparated with an insulation layer 5 from one another and from theintegrated circuit 1 to be protected. An electrical short between theinterconnects 10, 11 and the integrated circuit 1 is prevented by thisinsulation layer.

The interconnects 10 are fashioned stripe-shaped in the first circuitlevel 2 and are separated from one another by stripe-shaped insulationregions 6. The interconnects 10 are arranged parallel to one another inthe first circuit level 2. A second circuit level 3 that exhibitscorresponding, stripe-shaped interconnects 11 arranged parallel to oneanother is arranged above the circuit level 2. These interconnects 11are also separated from one another by insulation regions 6 and are thusinsulated from one another. The interconnects 10 are arranged such that,in cooperation with the interconnects 11, they completely cover theintegrated circuit to be protected. This complete coverage is achievedwhen, looking through the first and second circuit level 2, each pointof the integrated circuit to be protected or, respectively, each pointto be protected in the integrated circuit 1 is covered either by theinterconnects 10 or by the interconnects 11 or both by the interconnects10 as well as the interconnects 11.

When someone wishes to access the integrated circuit 1 to be protected,then he must first penetrate the protective circuit and thereby punchthrough the circuit levels 2, 3 and damage at least one of theinterconnects 10, 11 since the integrated circuit is completely covered.Such damage, which, for example, can represent a complete interruptionof the interconnects or a short between the interconnects in one circuitlevel 2, 3 or between the circuit levels 2, 3 or merely a partialdestruction of the interconnect 10, 11, leads to a clear modification ofthe transmitted signal. This transmitted signal is compared to theanticipated reference signal by the allocated detector, and isinterpreted as an error signal and, thus, as an attack on the protectivecircuit or, respectively, on the integrated circuit 1 to be protected,which leads to the output of an alarm signal to the integrated circuit1. This alarm signal then switches the integrated circuit 1 into thesecurity mode.

The generators 20, 21, 22 (not shown here) or the correspondingdetectors 30 through 36 (not shown here) are arranged in the firstcircuit level 2 protected by the circuit level 3 lying above it with thecorrespondingly arranged interconnects 11. This arrangement may bedistributed over the entire first circuit level 2, which clearlyrestricts the possibilities of defeating the protective circuit.

FIG. 4 shows an exemplary embodiment of a development of the inventionwith eight interconnects 40 . . . 47. These eight interconnects 40 . . .47 are subdivided into two groups of four interconnects 40 . . . 43 and44 . . . 47. Only one signal generator 60 or, respectively, 62 and onesignal detector 61 or, respectively, 63 is allocated to each of the twogroups. The signals of the signal generators 60, 62 are supplied to theinterconnect groups 40 . . . 43 or, respectively, 44 . . . 47 viademultiplexers 50 or, respectively, 52, and the signals transmitted viathe interconnects are supplied to the signal detectors 61 or,respectively, 63 via multiplexers 51 or, respectively, 53.

In order to be able to supply the signal detectors 61, 63 with therequired reference signals, only one connecting line 48 or,respectively, 49 is required per interconnect group given thisdevelopment of the invention. The signal detectors 61, 63 also indicatewhen the signal received via the multiplexers 51, 53 does not agree withthe anticipated signal via the alarm lines 4.

Two different possibilities for driving the demultiplexers 50, 52 andmultiplexers 51, 53 are shown given the illustrated exemplary embodimentwith two interconnect groups 40 . . . 43 and 44 . . . 47. Given theinterconnect group 40 . . . 43 shown in the upper part of FIG. 2, thedemultiplexer 50 and the multiplexer are driven in common by a truerandom number generator 70 to select one of the interconnects 40 . . .43. Given the interconnect group 44 . . . 47 shown below it theappertaining demultiplexer and the appertaining multiplexer 53 aredriven by two different, but identically fashioned pseudo-random numbergenerators 71, 72 that, due to their identical structure, supply thesame random numbers at the same points in time given common clocking.Fundamentally, however, it is also possible to drive the demultiplexers50, 52 and multiplexers 51, 53 with a clock signal itself, which issimpler in circuit-oriented terms but less secure. With a given chiparea, a good compromise between optimally complete coverage of the chipsurface with optimally narrow and closely adjacent interconnects and thewish for optimally little circuit-oriented expenditures can be found onthe basis of this inventive development of a protective circuit.

The above-described circuit is illustrative of the principles of thepresent invention. Numerous modifications and adaptions thereof will bereadily apparent to those skilled in this art without departing from thespirit and scope of the present invention.

What is claimed is:
 1. A protective circuit for an integrated circuit,wherein said protective circuit is arranged in a circuit level at alocation under or above said integrated circuit, said protective circuitcomprising: a plurality of interconnects that are charged with differentsignals of a signal generator; a detector that evaluates said differentsignals transmitted via said plurality of interconnects for faultybehavior, said detector having an output at which, when said faultybehavior is found, a control signal is provided for switching saidintegrated circuit into a security mode; a demultiplexer connected toone end of a first group of said plurality of interconnects, saiddemultiplexer combining said group of plurality of interconnects; arespective multiplexer connected to an other end of said group of saidplurality of interconnects; a single signal generator that is connectedto said demultiplexer; a single signal detector that is connected tosaid multiplexer; a selection signal generator that drives an entityselected from the group consisting of said multiplexer and saiddemultiplexer; and a demultiplexer connected to one end of a first groupof said plurality of interconnects, said demultiplexer combining saidgroup of a plurality of interconnects.
 2. A protective circuit accordingto claim 1, wherein said plurality of interconnects are extended over aplurality of circuit levels of said protective circuit.
 3. A protectivecircuit according to claim 1, wherein said interconnects are fashionedsuch that said integrated circuit is largely covered to prevent accesswithout damage to said integrated circuit or interruption of one of saidplurality of interconnects.
 4. A protective circuit according to claim1, wherein said plurality of interconnects are fashioned with a narrowwidth so that they will be interrupted by an intrusion attempt.
 5. Aprotective circuit according to claim 1, wherein said detector isarranged in a circuit level under a circuit level with said plurality ofinterconnects and protected against access by these interconnects.
 6. Aprotective circuit according to claim 1, wherein said generator isarranged in a circuit level under a circuit level with said plurality ofinterconnects and protected against access by these interconnects.
 7. Aprotective circuit according to claim 1, wherein said different signalsare generated independently of one another.
 8. A protective circuitaccording to claim 1, wherein said generator for different signals arefashioned such that said signals dynamically vary over time.
 9. Aprotective circuit according to claim 1, further comprising a pluralityof detectors that are allocated to one of said plurality ofinterconnects and a signal on this interconnect can be monitored.
 10. Aprotective circuit according to claim 1, wherein said selection signalgenerator is a random number generator.
 11. A protective circuitaccording to claim 1, wherein said selection signal generator is apseudo-random number generator.
 12. A protective circuit is according toclaim 1, further comprising multiple detectors that are networked withone another.
 13. A protective circuit according to claim 1, furthercomprising multiple signal generators that are networked with oneanother.
 14. A protective circuit according to claim 1, wherein saidintegrated circuit is surrounded by a plurality of circuit levels ofsaid protective circuit, one of said plurality of circuit levels beingabove said integrated circuit, and one of said plurality of circuitlevels being below said integrated circuit.
 15. A protective circuitaccording to claim 1, further comprising a unit for determining anintegrity value of a signal supplied to said detector, and saidintegrity value is interpreted for detecting a faulty behavior.
 16. Aprotective circuit for an integrated circuit, whereby the protectivecircuit is arranged in one or more circuit levels located in at leastone position consisting of under and over the integrated circuit, theprotective circuit comprising: at least one interconnect that is chargedwith at least one signal of at least one signal generator; and at leastone detector that evaluates the at least one signal transmitted via theat least one interconnect for faulty behavior, and is configured so thatwhen this faulty behavior is found, it can output a control signal forswitching the integrated circuit into a security mode, wherein the atleast one signal generator is configured to randomly select a type ofthe at least one signal and transmits a signal indicative of the type ofthe at least one signal to the at least one detector.